1. Field of the Invention
The present invention relates to a dynamic semiconductor memory cell having a field effect transistor which has a gate applied insulated to the boundary surface of a semiconductor body and two regions oppositely doped with respect to a basic doping of the semiconductor body, and a memory capacitor which likewise exhibits an oppositely doped first zone of the semiconductor body adjacent to the boundary surface and an electrode applied insulated to the boundary surface, in which the one region is connected to a bit line and the other is connected to the first zone, and to a method for manufacturing the same.
2. Description of the Prior Art
Memory cells of the type mentioned above are described, for example, in U.S. Pat. No. 3,533,089. In order to achieve greater and greater integration densities, there is an attempt in semiconductor memory technology to place the individual memory cells on as small as possible a semiconductor surface.